Method of fabricating metal-oxide-semiconductor transistor

Details Method of fabricating metal-oxide-semiconductor transistor Method of fabricating metal-oxide-semiconductor transistor

1998-06-09

2000-06-13

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438303, 438583, 438683, 438687, 438688, H01L 21336, H01L 2144

Patent

active

060749237

ABSTRACT:
A method of manufacturing a MOS transistor begins with the provision of a semiconductor substrate. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Next, the gate oxide layer, the polysilicon layer and the silicon nitride layer are patterned to form a gate structure. Subsequently, spacers are formed covering the sidewalls of the gate oxide layer, the polysilicon layer and the silicon nitride layer. Thereafter, a dielectric layer is formed, and covers the semiconductor substrate, the silicon nitride layer and the spacers. Next, a planarization operation is carried out to remove a portion of the dielectric layer. Planarization continues until the silicon nitride layer is exposed. After that, the silicon nitride layer is removed, exposing the polysilicon layer, and then a glue layer is formed over the dielectric layer and the polysilicon layer. Finally, a conductive layer is formed over the glue layer to complete the fabrication of the MOS transistor.

REFERENCES:
patent: 5950090 (1999-09-01), Chen et al.
patent: 5981365 (1999-11-01), Cheek et al.
patent: 5994192 (1999-11-01), Chen

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