Method for forming planar field effect transistors with source a

Details Method for forming planar field effect transistors with source a Method for forming planar field effect transistors with source a

1999-08-17

2000-11-14

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257353, 257354, 257385, 257386, 257 66, H01L 2701, H01L 2976

Patent

active

061473847

ABSTRACT:
A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor body. The first void region is separated from the second void region by a portion of the semiconductor body (10). The method further includes depositing a dielectric material in the first void region to form a first insulating region (16) and depositing a dielectric material in the second void region to form a second insulating region (16). The method further includes planarizing the first and second insulating regions to define a planar surface (17). The method also includes forming a conductive source region (34) overlying the first insulating region, forming a conductive drain region (36) overlying the second insulating region, and forming a conductive gate body (24) overlying the planar surface and spaced apart from the conductive source region and the conductive drain region.
A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed on the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).

REFERENCES:
patent: 4041518 (1977-08-01), Shimizu et al.
patent: 4251828 (1981-02-01), Sakurai
patent: 4487639 (1984-12-01), Lam et al.
patent: 4654958 (1987-04-01), Baerg et al.
patent: 5213991 (1993-05-01), Inokawa et al.
patent: 5712495 (1998-01-01), Suzawa
IEDM 1985, "A Novel MOS Device Structure with S/D Contacts Over Oxide (COO)", pp. 204-207 (C.H. Dennison, et al.).
1996 Symposium on VLSI Technology Digest of Technical Papers, "O.15 .mu.m Delta-Doped CMOS With On-Field Source/Drain Contacts", pp. 172-173 (K. Imai, et al.).

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