Low power, high speed communications bus

Details Low power, high speed communications bus Low power, high speed communications bus

1998-05-18

2000-10-31

Follansbee, John A.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

G06F 1342

Patent

active

061417653

ABSTRACT:
A low power, high speed communications bus is provided which may interconnect semiconductor dies or computer modules over short distances. The bus may be operated in either a mesosynchronous mode of operation or asynchronous mode of operation so that the bus does not require a phase locked loop (PLL). In addition, the bus does not require termination due to the programmed `series termination` in combination with strict limits on the time of flight on the bus versus the slew rate of the signals. The bus may also permit the port sizes connected to the bus to be reconfigured on the fly to provide "quality of service support for buses". The bus may also provide multiple independent data streams that may be controlled by a single address/command bus. The bus may also provide a pair of wires which carry two signals (e.g., a TStrb/Ren signal on one wire and a RStrb/Ten signal on the other wire) between each port to communicate the strobe signals between the ports.

REFERENCES:
patent: 5034967 (1991-07-01), Cox et al.
patent: 5280623 (1994-01-01), Sodos et al.

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