Semiconductor device having self-aligned asymmetric source/drain

Details Semiconductor device having self-aligned asymmetric source/drain Semiconductor device having self-aligned asymmetric source/drain

1998-10-01

2000-11-14

Zarabian, Amir

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

257401, H01L 21336

Patent

active

061469521

ABSTRACT:
A semiconductor device and manufacturing method is provided in which asymmetric source/drain regions are formed using a self aligning implant mask. A gate electrode is formed on a substrate and a dielectric layer is formed over the substrate and adjacent the gate electrode. A masking layer is formed over the dielectric layer and the gate electrode and selectively removed to form an implant mask. The implant mask extends further over a first side of the gate electrode than a second side of the gate electrode. Using the implant mask for alignment, a dopant is implanted into the active regions of the substrate adjacent the gate electrode to form a first heavily-doped region adjacent the first side of the gate electrode and second heavily-doped region adjacent the second side of the gate electrode. The first heavily-doped region is spaced further from the gate electrode than the second heavily-doped region. Contacts may be formed to the masking layer or a silicide layer formed from the masking layer.

REFERENCES:
patent: 5296398 (1994-03-01), Noda
patent: 5783457 (1998-07-01), Hsu
patent: 5893739 (1999-04-01), Kadosh et al.
S. Wolf and R.N. Tauber, Silicon Processing for the VLSI Era--Process Technology, (Lattice Press, California, 1986) pp. 321-327, 384-397.
S. Wolf, Silicon Processing for the VLSI Era--Process Integration, (Lattice Press, California, 1990) pp. 238-239.

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