Method for manufacturing a vertical mosfet including a back gate

Details Method for manufacturing a vertical mosfet including a back gate Method for manufacturing a vertical mosfet including a back gate

1997-04-17

1999-02-16

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, 438279, 438283, 438284, 438154, H01L 21336

Patent

active

058720375

ABSTRACT:
Semiconductor regions (2, 12) includes pillar-like projections (3, 13) extending vertically from major surfaces of the semiconductor regions and each having a vertical outer surface and an inner surface opposite to the outer surface. Vertical MOS transistors includes gate electrodes (4, 14) opposed to the outer surfaces of the pillar-like projections (3, 13) with gate insulating films (5, 15) interposed therebetween, with their bottom surfaces opposed to the major surfaces of the semiconductor regions (2, 12) with the gate insulating films (5, 15) interposed therebetween, source regions (6, 16) formed in upper end portions of the pillar-like projections (3, 13), drain regions (7, 17) formed in the major surfaces of the semiconductor regions (2, 12) so as to partly overlap bottom surfaces of the gate electrodes (4, 14), and back gate electrodes (8, 18) opposed to the inner surfaces of the pillar-like projections (3, 13) with back gate insulating films (9, 19) interposed therebetween. In the semiconductor device as above constructed, the MOS transistor can be supplied with a desired potential to avoid a punch through.

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