Method of manufacturing a split-gate flash memory cell

Details Method of manufacturing a split-gate flash memory cell Method of manufacturing a split-gate flash memory cell

1997-12-24

1999-02-16

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438593, H01L 218247

Patent

active

058720367

ABSTRACT:
A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

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patent: 5686333 (1997-11-01), Sato
patent: 5705416 (1998-01-01), Kim et al.
patent: 5716865 (1998-02-01), Ahn

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