Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-11-21
1999-02-16
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438398, 438DIG964, H01L 218242
Patent
active
058720332
ABSTRACT:
A method for forming a capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A second polysilicon layer is LO deposited at a temperature adjusted to cause a nucleation of the second polysilicon layer. As a result of the nucleation the second polysilicon layer is altered to resemble hemispherical grains. Next the first and second polysilicon layers are oxidized in an oxide/phosphine ambient. During the oxidation portions of the first and second polysilicon layers are consumed forming a phosphine rich oxygen layer on the surface of the hemispherical grains and in portions of the first polysilicon layer lying between the grains which are reduced in size due to the oxidation. A wet etch is then performed to remove the oxygen layer. Phosphorous ions are driven into the hemispherical grains during the oxidation thereby doping the grains. The oxidation is controlled such that the surface area of the hemispherical grains and first polysilicon layer retain a roughened surface area that is at least equal to a surface area of the hemispherical grains prior to the oxidation. The distance between the grains increases as a result of the oxidation. Following the etch a dielectric layer is deposited to overlie the rough polysilicon. A cell plate layer is deposited overlying the dielectric layer.
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Bowers Jr. Charles L.
Gurley Lynne A.
Micro)n Technology, Inc.
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