Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1999-12-08
2000-10-31
Zarabian, Amir
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
327538, G11C 1604
Patent
active
061412589
ABSTRACT:
The impedance of a pull-down output buffer circuit is adjusted to an integer multiple of the resistance value of an off-chip resistor with reference to the adjustment information obtained by adjusting the impedance of the pull-down dummy buffer circuits 13 and 14 to the resistance value of the off-chip resistor by means of a pull-down counter. The impedance of the pull-up output buffer circuit is adjusted to the pull-down dummy buffer circuit 14, i.e., an integer multiple of the resistance value of an off-chip resistor with reference to the adjustment information obtained by adjusting the impedance of the pull-up dummy buffer circuit to the impedance of the pull-down dummy buffer circuit 14 by means of a pull-up counter.
REFERENCES:
patent: 5355038 (1994-10-01), Hui
patent: 5576656 (1996-11-01), McClure
patent: 5596297 (1997-01-01), McClure et al.
patent: 5917335 (1999-06-01), Rees
Kabushki Kaisha Toshiba
Phung Anh
Zarabian Amir
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