Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-02-03
2000-10-03
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711144, 711145, 711146, G06F 1300
Patent
active
061287067
ABSTRACT:
Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardware cache to try to maintain ownership until the next memory reference from that processor. When used with the Cmpxchg instruction semaphore operation, the Load-Bias instruction will reduce coherency traffic, and minimize the possibility of coherency ping-ponging or system deadlock that causes the condition in which no processor is getting useful work done.
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Bryg William R.
Burger Stephen G.
Hammond Gary N.
Ziegler Michael L.
Cabeca John W.
Institute for the Development of Emerging Architectures L.L.C.
Tzeng Fred F.
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