Process for forming integrated circuit structure with metal sili

Details Process for forming integrated circuit structure with metal sili Process for forming integrated circuit structure with metal sili

1997-08-28

1998-12-22

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438592, 438595, 438655, H01L 21335

Patent

active

058518908

ABSTRACT:
A process for forming improved metal silicide contacts over the gate electrode and source/drain regions of MOS devices of an integrated circuit structure formed in a silicon substrate is described. The metal silicide contacts are formed by first forming a silicon oxide layer over exposed portions of the silicon substrate and over exposed surfaces of previously formed polysilicon gate electrodes. Silicon nitride sidewall spacers are then formed over the oxide on the sidewalls of the gate electrode by depositing a silicon nitride layer over the entire structure and then anisotropically etching the silicon nitride layer. Source/drain regions are then formed in the silicon substrate adjacent the nitride spacers and the structure is then contacted with an oxide etch to remove oxide from the upper surface of the gate electrode and the substrate surface over the source/drain regions. During the oxide etch step, notches, each having an aspect ratio of 1 or less, are formed in the exposed edges of the oxide respectively between the silicon nitride spacers and either the substrate or the gate electrode. A metal layer capable of reacting with the exposed silicon to form metal silicide contacts is then blanket deposited over the structure and into the notches. After reacting the metal with silicon surfaces with which it is in contact to form metal silicide, the unreacted metal is removed, leaving a metal silicide gate contact on the upper surface of the polysilicon gate electrode, as well as those upper portions of the sidewall of the gate electrode exposed by forming the notch in the oxide layer on the sidewall of the electrode. Metal silicide source/drain contacts of enlarged area are also formed over the exposed silicon surfaces of the source/drain regions and those portions of the silicon substrate beneath the nitride spacers exposed by the notches formed in the oxide beneath the nitride spacers.

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Fornara, P., et al., "Modeling of Local Reduction in TiSi.sub.2 and CoSi.sub.2 Growth Near Spacers in MOS Technologies: Influence of Mechanical Stress and Main Diffusing Species", IEDM, vol. 96, 1996, pp. 73-76.
Mazure, Carlos, et al., "Impact of LDD Spacer Reduction on MOSFET Performance for Sub-.mu.m Gate/Space Pitches", IEDM, vol. 92, 1992, pp. 893-896.

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