Single event upset hardened CMOS latch circuit

Details Single event upset hardened CMOS latch circuit Single event upset hardened CMOS latch circuit

1995-02-01

1996-04-02

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Flip-flop

365194, 36518905, G11C 11412

Patent

active

055047033

ABSTRACT:
SEU immunity is provided in a cross-coupled CMOS latch circuit by inserting a pair of series connected invertors between the drain node of one CMOS invertor and the gate node of the other CMOS invertor and a pair of series connected invertors between the drain node of the other CMOS invertor and the gate node of the one CMOS invertor. The invertor pairs delay the propagation of a change in voltage induced by an energetic ion strike at the off drain of one invertor to the gates of the transistors making up the other cross coupled invertor. The invertor connected to the gates of the transistors affected by the ion strike help in restoring the circuit to its original state.

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