Dynamic folding of cache operations for multiple coherency-size

Details Dynamic folding of cache operations for multiple coherency-size Dynamic folding of cache operations for multiple coherency-size

1997-04-14

2000-08-15

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711139, 711144, G06F 1200

Patent

active

061051128

ABSTRACT:
A method is disclosed of managing architectural operations in a computer system whose architecture includes components having varying coherency granule sizes. A queue is provided for receiving as entries a plurality of the architectural operations, the entries of the queue are compared with a new architectural operation to determine if the new architectural operation is redundant with any of the entries. If the new architectural operation is not redundant with any of the entries, it is loaded in the queue. The computer system may include a cache having a processor granularity size and a system bus granularity size which is larger than the processor granularity size, and the architectural operations are cache instructions. The comparison may be performed in an associative manner based on the varying coherency granule sizes.

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