Excavating
Patent
1992-11-24
1995-11-28
Baker, Stephen M.
Excavating
H03M 1300
Patent
active
054714850
ABSTRACT:
A power sum computation unit for a Reed-Solomon decoder having r redundant symbols and in which a code word, R, has a first plurality (n) of symbols, each symbol having a plurality (m) of bits, including multiplier unit for multiplying in parallel M symbols by powers of a finite field element, .alpha., to obtain the power sums ##EQU2## The multiplier unit includes M multipliers for multiplying M symbols by powers of alpha, and memory delay including a latch, a random access memory, and a flipflop store symbols and sequentially provide M symbols to the multiplier unit. Exclusive OR gate selectively connects products from the multiplier unit and data input words to the memory delay. A counter is provided for the random access memory with the counter having a modulo number equal to one less than r/M, and the random access memory having a depth equal to one less than r/M.
REFERENCES:
patent: 4680764 (1987-07-01), Suzuki et al.
patent: 4763332 (1988-08-01), Glover
patent: 4777635 (1988-10-01), Glover
Tong, Po "A 40-MHz Encoder-Decoder Chip Generated by a Reed-Solomon Code Compiler," IEEE 1990 Custom Integrated Circuits Conference, pp. 13.5.1-13.5.4.
Baker Stephen M.
LSI Logic Corporation
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