Semiconductor memory device permitting high speed data transfer

Details Semiconductor memory device permitting high speed data transfer Semiconductor memory device permitting high speed data transfer

1994-09-13

1996-12-17

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365149, 365 63, 36523003, G11C 700, G11C 1124

Patent

active

055860761

ABSTRACT:
In a memory cell array, data lines are formed into a hierarchical arrangement of sub data lines provided for every block and a main data line common to each block, and a sub data line selected by a column address among sub data lines belonging a block which are simultaneously selected by a row address is connected to a bit line. Accordingly, the sub data line length is reduced, which reduces floating capacitance, reading and writing operations can be conducted at a high speed, and sub data lines can be selectively operated. In addition, power required for charging the sub data lines can be reduced, and entire power consumption by the semiconductor memory device can be reduced as well.

REFERENCES:
patent: 4748591 (1988-05-01), Itoh et al.
patent: 5097440 (1992-03-01), Konishi
patent: 5321657 (1994-06-01), Arimoto et al.
patent: 5418737 (1995-05-01), Tran
"A 40-ns 64-Mo DRAM with 64-b Parallel Data Bus Architecture" Taguchi et al., IEEE Journal of Solid-State Circuits, vol. 26, No. 11m, Nov. 1991.

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