Modulated slope signal generation circuit, particularly for latc

Details Modulated slope signal generation circuit, particularly for latc Modulated slope signal generation circuit, particularly for latc

1996-07-19

1998-04-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, 365204, 365203, 365205, G11C 700

Patent

active

057372683

ABSTRACT:
A latch arrangement, having a load, receives an equalization signal to control the timing of data sensing and data capture. The slope of the equalization signal is modulated so that it has two slopes: a less steep one which permits evaluation of a datum with appropriate caution, and a much steeper slope, which occurs at the end of reliable evaluation, to capture the datum and store it. The equalization signal is generated by first presetting the equalization signal to a first value. Thereafter a change in the equalization signal from the first value to a second value is initiated. After initiating the change in the equalization signal, the equalization signal is slowly discharged at a first slope. A ratio between a current generated in a generic matrix cell applied to the load of the latch arrangement and a reference current is evaluated. When the evaluated ratio reaches a desired level, the equalization signal is quickly discharged to the second value at a second slope.

REFERENCES:
patent: 3848236 (1974-11-01), Troutman
patent: 4669063 (1987-05-01), Kirsch
patent: 4811290 (1989-03-01), Watanabe
patent: 5541881 (1996-07-01), Miller
patent: 5598376 (1997-01-01), Merritt et al.
European Search Report from European Patent Application No. 95830336.4, filed Jul. 28, 1995.

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