Method to reduce gate-to-local interconnect capacitance using a

Details Method to reduce gate-to-local interconnect capacitance using a Method to reduce gate-to-local interconnect capacitance using a

1999-08-17

2000-10-24

Smith, Matthew

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257340, 257386, 257900, 438303, H01L 2972, H01L 2710, H01L 21336

Patent

active

061371262

ABSTRACT:
The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.

REFERENCES:
patent: 4769686 (1988-09-01), Horiuchi et al.
patent: 5162882 (1992-11-01), Pollack
patent: 5608247 (1997-03-01), Brown
patent: 5744387 (1998-04-01), Tseng
patent: 5965934 (1999-10-01), Cheung et al.

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