Method of forming CMOS circuitry including patterning conductive

Details Method of forming CMOS circuitry including patterning conductive Method of forming CMOS circuitry including patterning conductive

1998-07-28

2000-10-24

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438226, 438262, 438672, 438702, H01L 218238

Patent

active

061366374

ABSTRACT:
A method for forming CMOS DRAM circuitry is disclosed and which includes forming a substrate comprising an array NMOS region, a peripheral NMOS region, and a peripheral PMOS region; forming a pair of insulated and spaced gate lines in the array NMOS region; forming at least one electrically conductive plug in the array NMOS region and which spans between the pair of gate lines; forming a barrier layer over the pair of gate lines in the array NMOS region, the peripheral NMOS and the peripheral PMOS region; and patterning and etching in the peripheral PMOS region to form peripheral PMOS region gate lines including removing a portion of the barrier layer in the PMOS peripheral region and leaving barrier layer material in the NMOS region masking over the electrically conductive plug

REFERENCES:
patent: 5112761 (1992-05-01), Mathews
patent: 5571733 (1996-11-01), Wu et al.
patent: 5624863 (1997-04-01), Helm et al.
patent: 5811329 (1998-09-01), Ahmad et al.
patent: 5840621 (1998-11-01), Kasai

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