Method of manufacturing deep sub-micron CMOS transistors

Details Method of manufacturing deep sub-micron CMOS transistors Method of manufacturing deep sub-micron CMOS transistors

1999-04-14

2000-10-24

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438233, 438305, 438558, 438564, H01L 218238, H01L 21336

Patent

active

061366366

ABSTRACT:
The present invention includes forming nitrogen-doped amorphous silicon layer on the gate structure and on a pad oxide. Nitride spacers are formed on the side walls of the gate structure. Then, the nitride spacers and the cap nitride are both removed by wet etching. Next, an ion implantation is carried out to dope dopants into the gate and in the N well. Doped regions for the NMOS device are next formed in the P well by performing a further ion implantation. An oxidation is performed to convert the nitrogen-doped amorphous silicon layer to a nitrogen-doped oxide layer. An ultra-shallow source and drain junctions and the extended source and drain are obtained by using the amorphous silicon layer as a diffusion source. Next, nitrogen spacers on the side walls of the oxide are formed. The oxide on the top of the gate and uncovered by the spacers are removed during the etching to form spacers. Self-aligned silicide (SALICIDE) and polycide are respectively formed on the exposed substrate and gate.

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