Semiconductor memory utilizing RAS and CAS signals to control th

Details Semiconductor memory utilizing RAS and CAS signals to control th Semiconductor memory utilizing RAS and CAS signals to control th

1995-04-10

1996-09-03

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, 365233, G11C 11407, G11C 700

Patent

active

055530249

ABSTRACT:
An improved semiconductor memory device such as a dynamic random access memory (DRAM) includes a latch circuit and an output buffer. The latch circuit latches first data read out from one memory cell of a memory cell array during one cycle of a row address strobe (RAS) signal and during one cycle of a column address strobe (CAS) signal. During another cycle of the row address strobe signal and during another cycle of the column address strobe signal, the first data is transferred from the latch circuit to the output buffer and the latch circuit latches second data read out from another memory cell of the memory cell array. The use of the latch circuit and output buffer reduces access time and increases the data transfer rate of the memory device.

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