Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-03-17
1999-02-09
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, 438252, H01L 218242
Patent
active
058693670
ABSTRACT:
A method of forming a capacitor includes, a) providing a series of alternating first and second layers of semiconductive material over a node location, a first of the first and second layers having an average conductivity enhancing dopant concentration of greater than about 5.times.10.sup.19 ions/cm.sup.3, a second of the first and second layers having an average conductivity enhancing dopant concentration from 0 ions/cm.sup.3 to about 5.times.10.sup.19 ions/cm.sup.3, at least one of the first and second layers being selectively etchable relative to the other of the first and second layers; b) providing a contact opening through the first and second layers of semiconductive material to the node location; c) providing an electrically conductive within the contact opening; d) masking and etching the conductive layer and the series of alternating layers to form a first capacitor plate; e) etching the one of the first and second layers at a faster rate than the other of the first and second layers to define lateral projections of the other of the first and second layers relative to the one of the first and second layers, the electrically conductive layer being in ohmic electrical connection with the first and second layers and lateral projections thereof; the conductive layer, the first and second layers and lateral projections thereof comprising the first capacitor plate; f) providing a capacitor dielectric layer over the conductive layer and the lateral projections; and g) providing a second capacitor plate over the capacitor dielectric layer.
REFERENCES:
patent: 5005072 (1991-04-01), Gonzalez
patent: 5006481 (1991-04-01), Chan et al.
patent: 5021357 (1991-06-01), Taguchi et al.
patent: 5061651 (1991-10-01), Ino
patent: 5071781 (1991-12-01), Seo et al.
patent: 5116776 (1992-05-01), Chan et al.
patent: 5126810 (1992-06-01), Gotou
patent: 5135883 (1992-08-01), Bae et al.
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5170233 (1992-12-01), Liu et al.
patent: 5223729 (1993-06-01), Kudoh et al.
patent: 5290726 (1994-03-01), Kim
patent: 5622882 (1997-04-01), Yee
patent: 5631184 (1997-05-01), Ikemasu et al.
Ema, T., et al., "3-Dimensional Stacked Capacitor Cell For 16M and 64M Drams", IEDM 1988, pp. 592-595.
Temmler, D., "Multilayer Vertical Stacked Capacitors (MVSTC) For 64Mbit and 256 Mbig DRAMs", Article, no date, pp., 13-14. date unknow.
Inoue, S., et al., "A Spread Stacked Capacitor (SSC) Cell For 64Mbit DRAMs", IEEE 1989, pp. 31-34 (2.3.1-2.3.4).
Morihara, Toshinori et al., "Disk-Shaped Stacked Capacitor Cell for 256 Mb Dynamic Random-Access Memory", Jpn. J. Appl. Phys., vol. 33 (1994) Pt. 1, No. 8.
Watanabe, Hidehiro, et al., "Stacked Capacitor Cells for High-Density RAMs", IEDM 88, pp. 600-603. date unknown.
S.H. Woo, et al., "Selective Etching Technology of in-situ P Doped Poy-Si (SEDOP) for High Density DRAM Capacitors", IEEE, 1994, pp. 25-26.
Fazan Pierre C.
Keeth Brent
Micro)n Technology, Inc.
Tsai Jey
LandOfFree
Method of forming a capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1948115