Method of forming buried bit line

Details Method of forming buried bit line Method of forming buried bit line

1999-11-06

2000-10-03

Quach, T. N.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438149, 438296, 438672, H01L 21336

Patent

active

061272280

ABSTRACT:
A method of forming buried bit lines. A silicon-on-insulator (SOI) substrate includes a silicon base layer, a first insulation layer and an epitaxial silicon layer. A shallow trench isolation (STI) layer that contacts the first insulation layer is formed in the epitaxial silicon layer. A trench that penetrates the STI layer and runs deep into the first insulation layer is formed. A buried bit line is formed inside the trench such that the top surface of the buried bit line is located between the upper and the lower surface of the STI layer. A second insulation layer is next formed over the buried bit line such that the top surface of the second insulation layer is at the same level as the top surface of the epitaxial silicon layer. A plurality of word lines and a plurality of source/drain regions are formed over the substrate and in the epitaxial silicon layer. A third insulation layer is formed over the substrate, filling the space between the word lines such that the top surface of the third insulation layer is at the same level as the top surface of the word lines. A self-aligned contact process is carried out to form a bit line contact opening between the word lines. The bit line contact opening exposes the buried bit line and a portion of the source/drain region. Finally, bit line contact is formed in the bit line contact opening.

REFERENCES:
patent: 5702969 (1997-12-01), Lee
patent: 5753551 (1998-05-01), Sung
patent: 5830797 (1998-11-01), Cleeves
patent: 5840591 (1998-11-01), Park et al.
patent: 6004835 (1999-12-01), Noble

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