Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Patent
1991-10-16
2000-02-15
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
714718, 714719, G06F 1100
Patent
active
060265051
ABSTRACT:
A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.
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Hedberg Erik Leigh
Koch Garrett Stephen
International Business Machines - Corporation
Le Dieu-Minh T.
Walsh Robert A.
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