Method of fabricating high-conductivity silicide-on-polysilicon

Details Method of fabricating high-conductivity silicide-on-polysilicon Method of fabricating high-conductivity silicide-on-polysilicon

1981-01-19

1982-12-07

Lawrence, Evan K.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 156657, 1566591, 1566611, 357 71, H01L 21308, H01L 21314

Patent

active

043625975

ABSTRACT:
It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

REFERENCES:
patent: 4004044 (1977-01-01), France et al.
patent: 4244799 (1981-01-01), Fraser et al.
Morau, J. M. and Maydau, D., High Resolution, Steep Profile, Resist Patterns, The Bell System Technical Journal, 58(5): pp. 1027-1036, May-Jun. , 1979.
Murarka, S. P., et al., Refractory Silicides of Titanium and Tautalum for Low-Resistivity Gates and Interconnects, IEEE (Journal of Solid-State Circuits, SC-15(4): pp. 474-482, Aug. 1980.

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