Selective diffusion process for forming both n-type and p-type g

Details Selective diffusion process for forming both n-type and p-type g Selective diffusion process for forming both n-type and p-type g

1996-06-28

1998-07-14

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438532, 438919, H01L 218238

Patent

active

057803307

ABSTRACT:
First and second conductivity type regions are produced in a polysilicon layer using only a single masking step. In one embodiment, the polysilicon layer is doped to a first conductivity type. A first oxide layer is then formed and patterned over the polysilicon layer to cover a first region and expose a second region of the polysilicon layer. The exposed second region of the polysilicon layer is then counter-doped, with the first oxide layer acting as a mask to prevent counter-doping of the underlying first region of the polysilicon layer. In accordance with the present invention, n-channel devices with n-type or p-type polysilicon gates and p-channel devices with p-type or n-type polysilicon gates can be formed without having to add a single process step. Thus, n-channel and p-channel devices with two different threshold voltages can be realized without adding a single process step.

REFERENCES:
patent: 4555842 (1985-12-01), Levinstein et al.
patent: 4637836 (1987-01-01), Flatley et al.
patent: 4703552 (1987-11-01), Baldi et al.
patent: 5021356 (1991-06-01), Henderson et al.
patent: 5278085 (1994-01-01), Maddox, III et al.
patent: 5393679 (1995-02-01), Yang

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