Semiconductor processing methods of forming complementary metal

Details Semiconductor processing methods of forming complementary metal Semiconductor processing methods of forming complementary metal

1996-06-25

1998-05-19

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257376, 257378, H01L 2704, H01L 2970

Patent

active

057539561

ABSTRACT:
A semiconductor processing method of forming complementary metal oxide semiconductor memory circuitry includes, a) defining a memory array area and a peripheral area on a bulk semiconductor substrate, the peripheral area including a p-well area for formation of NMOS peripheral circuitry, the peripheral area including a first n-well area and a second n-well area for formation of respective PMOS peripheral circuitry, the first and second n-well areas being separate from one another and having respective peripheries; b) providing a patterned masking layer over the substrate relative to the peripheral first and second n-wells, the masking layer including a first masking block overlying the first n-well and a second masking block overlying the second n-well, the first masking block masking a lateral edge of the first n-well periphery; and c) with the first and second masking blocks in place, providing a buried n-type electron collector layer by ion implanting into the bulk substrate; the resultant n-type electron collector layer implant extending to the second n-well periphery to be in electrical connection therewith; the resultant n-type electron collector layer implant being spaced from the first n-well periphery for preventing electrical connection with the first n-well. Memory devices and other circuitry are also disclosed.

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