Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1991-12-27
1993-11-23
Dixon, Joseph L.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 371 102, 371 103, G11C 2900, G11C 700
Patent
active
052650553
ABSTRACT:
A redundancy technique is introduced for a semiconductor memory and, more particularly a redundancy technique for a dynamic random access memory (DRAM) having a storage capacity of 16 mega bits or more. In such a DRAM, the efficiency of the redundancy technique is reduced, since a memory array is divided into a large number of memory mats. According to the present redundancy technique, in a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, and memory cells disposed at desired ones of the two-level crossings, there is provided, furthermore, a plurality of spare word (or bit) lines, address comparing circuits for storing therein a defective address existing in the memory array, to compare an address to be accessed with the defective address, and selection circuitry for replacing a word or bit line including a defective memory cell by a spare word (or bit) line in accordance with the result of the comparison. The memory array of the semiconductor memory is divided into M memory mats (where M .gtoreq.2), the number m of word or bit lines which are simultaneously replaced by spare word (or bit) lines, is less than the number M and equal to a divisor thereof, and the number L of spare word (or bit) lines per one memory mat and the number R of address comparing circuits satisfy a relation L<R.ltoreq.LM/m and, preferably, L<R<LM/m.
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Aoki Masakazu
Etoh Jun
Horiguchi Masashi
Itoh Kiyoo
Dixon Joseph L.
Hitachi , Ltd.
Lane Jack A.
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