Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-02-24
2000-05-23
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438216, H01L 218238
Patent
active
060665211
ABSTRACT:
In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region. Then, the polycrystalline silicon layer is patterned to form an emitter electrode. Then, a gate insulating layer is formed on the second semiconductor layer, and a gate electrode is formed on the gate insulating layer. Finally, a base graft region is formed type in the first semiconductor layer and source/drain regions are formed in the second semiconductor layer.
REFERENCES:
patent: 3775192 (1973-11-01), Beale
patent: 4313255 (1982-02-01), Shinozaki et al.
patent: 4839302 (1989-06-01), Kameyama et al.
patent: 4968635 (1990-11-01), Hamasaki
patent: 5254485 (1993-10-01), Segawa et al.
patent: 5319234 (1994-06-01), Uga et al.
patent: 5376562 (1994-12-01), Fitch et al.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986. p. 265.
Komuro Toshio
Yokoyama Hiroaki
Bowers Charles
Brewster William M.
NEC Corporation
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