Method of manufacturing electrically erasable semiconductor non-

Details Method of manufacturing electrically erasable semiconductor non- Method of manufacturing electrically erasable semiconductor non-

1996-03-22

1999-09-07

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438263, H01L 21336

Patent

active

059500859

ABSTRACT:
A method of manufacturing an electrically erasable semiconductor non-volatile memory device comprises forming a field insulating film on a surface of a semiconductor substrate having a first conductivity type. A gate insulating film is formed on the surface of the semiconductor substrate. Source and drain regions having a second conductivity type are formed in the surface of the semiconductor substrate in spaced-apart relationship with each other by introducing impurity ions having the second conductivity type into the semiconductor substrate with an acceleration energy sufficient to form a peak value of impurity concentration at a depth of more than approximately 500 .ANG. from the surface of the semiconductor substrate. The gate insulating film is then etched on the drain region to form a tunnel region having opposite sides connected to the field insulating film. Thereafter, a tunnel insulating film is formed on the tunnel region and a floating gate electrode is formed over the source region, the drain region and the semiconductor substrate through the gate insulating film and the tunnel insulating film. A control insulating film is then formed on the floating gate electrode, and a control gate electrode is formed over the floating gate electrode through the control insulating film.

REFERENCES:
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4831270 (1989-05-01), Weisenberger
patent: 5273923 (1993-12-01), Chang et al.
patent: 5316961 (1994-05-01), Okazawa
patent: 5453393 (1995-09-01), Bergemont
patent: 5656513 (1997-08-01), Wang et al.

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