Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1995-12-19
1998-12-08
Arroyo, Teresa M.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257635, 257649, 257754, 257774, H01L 2348, H01L 2352, H01L 2940, H01L 2358
Patent
active
058474609
ABSTRACT:
A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening. According to a further alternate embodiment, an etch stop layer is formed between the insulating layer and conductive region and an opening is formed in the insulating layer exposing the etch stop layer. A sidewall spacer film is formed over the insulating layer and the etch stop layer, both layers having a similar etch rate for a given etchant. The etch stop and spacer layers are etched in the opening to expose the underlying conductive layer thereby forming a contiguous sidewall spacer and etch stop layer on the sides of and under the insulating layer, thereby decreasing the contact dimension of the opening.
REFERENCES:
patent: 3801880 (1974-04-01), Harada et al.
patent: 4656732 (1987-04-01), Teng et al.
patent: 4677739 (1987-07-01), Doering et al.
patent: 4720908 (1988-01-01), Wills
patent: 4837183 (1989-06-01), Polito et al.
patent: 4960732 (1990-10-01), Dixit et al.
patent: 4962414 (1990-10-01), Liou et al.
patent: 4994410 (1991-02-01), Sun et al.
patent: 5067002 (1991-11-01), Zdebel et al.
patent: 5094979 (1992-03-01), Kusano
patent: 5106781 (1992-04-01), Penning De Vries
patent: 5117273 (1992-05-01), Stark et al.
patent: 5194929 (1993-03-01), Ohshima et al.
patent: 5270254 (1993-12-01), Chen et al.
patent: 5321211 (1994-06-01), Haslam et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5437763 (1995-08-01), Huang
patent: 5512785 (1996-04-01), Haver et al.
patent: 5604367 (1997-02-01), Yang
F.S. Chen, et al., "Planarized Aluminum Metallization for Sub-0.5 .mu.m CMOS Technology", IEDM, 1990, pp. 51-54.
V.V. Lee, et al, "Selective CVD Tungsten Local Interconnect Technology", IEDM, 1988, pp. 450-453.
Ono, et al., "Development of a Planarized A1-S1 Contact Filling Technology", Jun. 12-13, 1990 VMIC Conference, pp. 76-82.
Liou Fu-Tai
Zamanian Mehdi
Arroyo Teresa M.
Galanthay Theodore E.
Hill Kenneth C.
Jorgenson Lisa K.
STMicroelectronics Inc.
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