Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-01-06
2000-03-14
Cady, Albert De
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
060386916
ABSTRACT:
A test point analyzing apparatus determines a distinction between capability and incapability of insertion of a test point and a circuit modifying way when a test point is capable of being inserted for each of the test point types to each of the signal lines in a semiconductor integrated circuit by using circuit information, a test point insertion library, and test point insertion. Then, test point indexes to test point candidates capable of being inserted are calculated, and test point candidates having a large testability are selected based on the indexes, and the selected test point candidates are registered in test point information. Such processing is repeated until a predetermined condition of completing the test point analysis process is realized. In the apparatus, a test point index calculation portion calculates test point index information including CRF (Cost Reduction Factor) of each signal line from circuit information, determines a predetermined number of test point candidates in order of the CRF, and calculates COP (Controllability Observability Procedure, hereinafter referred to as test cost) when each of the test point candidates is assumed to be inserted. By setting candidates of the minimum COP as test points, a test point determining portion searches the other test point candidates not intersecting with an effect region of the test points in increasing order, and if there exists a test point candidate not intersecting with an effect region, the test point is added to a new test point group.
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Hatayama Kazumi
Hirano Jun
Nakao Michinobu
Cady Albert De
Hitachi , Ltd.
Lin Samuel
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