Integrated circuit binary data output interface for multiplexed

Details Integrated circuit binary data output interface for multiplexed Integrated circuit binary data output interface for multiplexed

1996-03-20

1999-09-07

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714734, 365201, G01R 3128

Patent

active

059481145

ABSTRACT:
Disclosed is an output interface for an integrated circuit permitting input and output pads to selectively receive binary data elements or electrical signals from multiple sources. The output interface contains a storage mechanism that stores the N binary information elements present on N internal lines of the integrated circuit and a multiplexer that presents the binary information in packets of K bits to a connection mechanism. Upon direction from a control mechanism, an insulation mechanism disconnects the pads from internal circuits on the chip, the connection mechanism connects the pads with the multiplexer, and the multiplexer sequentially makes the binary information available in packets of K bits to the K pads.

REFERENCES:
patent: 4929889 (1990-05-01), Seiler et al.
patent: 5469075 (1995-11-01), Oke et al.
patent: 5594694 (1997-01-01), Roohparvar et al.
patent: 5706235 (1998-01-01), Roohparvar et al.

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