Method for implementing priority encoders using FPGA carry logic

Details Method for implementing priority encoders using FPGA carry logic Method for implementing priority encoders using FPGA carry logic

1998-03-10

2000-06-27

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714725, 326 39, 326 41, G01R 3128, G06F 738, H03K 19177

Patent

active

060819146

ABSTRACT:
The invention provides a method for implementing an HDL-specified priority encoder as carry logic in an FPGA. A first embodiment of the method includes the steps of: 1) detecting an priority determination statement in the HDL code; 2) implementing the highest priority test in the statement using a first carry multiplexer; and 3) implementing the next highest priority test in the statement using another carry multiplexer that accepts the output of the preceding carry multiplexer as a carry input; and 4) repeating step 3 until each test in the statement has been implemented. Another embodiment of the invention includes the additional steps of: 1) counting the number of tests performed in the priority determination statement; and 2) comparing the number of tests to a set threshold criterion, to determine whether it is appropriate to implement the statement using carry logic.

REFERENCES:
patent: 5677638 (1997-10-01), Young et al.
patent: 5809035 (1998-09-01), Sikdar et al.
patent: 5870309 (1999-02-01), Lawman
patent: 5889411 (1999-03-01), Chaudhary
patent: 5910898 (1999-06-01), Johannsen
"The Programmable Logic Data Book" published Sep., 1996, pp. 4-11 to 4-23 and 4-184 to 4-190, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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