Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-01
2000-06-27
Dutton, Brian
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438238, 438235, 438239, 438240, 438254, 438255, 438396, 438397, 438398, H01L 218242, H01L 218234, H01L 218249
Patent
active
060806214
ABSTRACT:
A method of forming a DRAM capacitor that utilizes cap layers and spacers to surround the gate and bit line so that the necessary contact openings in a DRAM can be formed in two self-aligned contact processing operations. The capacitor of the DRAM is fabricated by forming contact node and openings within an insulating layer above a substrate, and then forming a first conductive layer conformal to the surface profile of the substrate above the substrate structure. Next, spacers are formed on the sidewalls of the conductive layer, and then a second conductive layer is formed filling the spacer between the spacers and over the substrate structure. Thereafter, a portion of the first conductive layer and the second conductive layer is removed to expose the spacers and the insulating layer. Finally, the spacers and the insulating layer are removed to expose a lower electrode structure that comprises the first and the second conductive layers.
REFERENCES:
patent: 5643819 (1997-07-01), Tseng
patent: 5702989 (1997-12-01), Wang et al.
patent: 5706164 (1998-01-01), Jeng
patent: 5726086 (1998-03-01), Wu
patent: 5744833 (1998-04-01), Chao
patent: 5763304 (1998-06-01), Tseng
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5792689 (1998-08-01), Yang et al.
patent: 5811331 (1998-09-01), Ying et al.
patent: 5851876 (1998-12-01), Jenq
patent: 5854105 (1998-12-01), Tseng
patent: 5923973 (1999-07-01), Chen et al.
patent: 5989952 (1999-10-01), Jen et al.
Jenq J. S. Jason
Wang Chuan-Fu
Dutton Brian
Huang Jiawei
Kebede Brook
Patents J. C.
United Microelectronics Corp.
LandOfFree
Method of manufacturing dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing dynamic random access memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1783754