Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Patent
1996-11-27
1998-12-08
Niebling, John
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
438770, H01L 2131
Patent
active
058468870
ABSTRACT:
Disclosed is a method for the shallow junction having a low sheet resistance and an improved electric characteristics, using the medium temperature CVD oxide layer deposited on the source/drain regions into which impurity ions are implanted. The medium temperature CVD oxide layer, which has a compressive stress of 1.53.times.10.sup.9 dyne/cm.sup.2, causes the surface of the silicon substrate to be subject to tensile stress. By forming the medium temperature CVD oxide layer on the silicon substrate at a temperature of approximately 760.degree.-820.degree. C., the defects in the inside of the substrate move to the surface of the silicon substrate. As a result, the concentration of the defects in the inside of the silicon substrate decreases so that the small size extended defects are on the surface of the silicon substrate. These extended defects can be naturally removed from the surface of the silicon substrate by performing a follow-up process such as a metalization or an additional thermal treatment process.
REFERENCES:
patent: 5030476 (1991-07-01), Okamura et al.
Cho Byung Jin
Lee Kil Ho
Hyundai Electronics Industries Co,. Ltd.
Lebentritt Michael S.
Niebling John
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