Method of increasing the capacitance area in DRAM stacked capaci

Details Method of increasing the capacitance area in DRAM stacked capaci Method of increasing the capacitance area in DRAM stacked capaci

1996-03-20

1997-01-07

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 47, 437919, 437233, H01L 218242

Patent

active

055916643

ABSTRACT:
A method is achieved for fabricating a dynamic random access memory (DRAM) storage capacitors having increased capacitance and reduced processing complexity. The capacitor bottom electrodes are made from a multilayer composed of alternately doped and undoped polysilicon layers formed by in-situ doping in a single LPCVD deposition step. The substrate is processed sequentially in the same etching chamber to pattern the multilayer in the RIE mode and then isotropically plasma etch to recess the doped polysilicon layer in the sidewalls of the multilayer. The recessing increases the surface area of the capacitor bottom electrode. The stacked storage capacitors are completed by forming a thin high dielectric constant insulator on the bottom electrode and a top polysilicon electrode. The method reduces processing complexity and manufacturing cost while providing capacitors with increased capacitance.

REFERENCES:
patent: 5286668 (1994-02-01), Chou
patent: 5374577 (1994-12-01), Tuan
patent: 5416037 (1995-05-01), Sato et al.
patent: 5441909 (1995-08-01), Kim
patent: 5459094 (1995-10-01), Jun

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