Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1992-03-11

1993-11-02

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

36518901, G11C 1300

Patent

active

052589579

ABSTRACT:
In a semiconductor memory device of a divided bit line system, read signals from memory cell blocks are sense-amplified together by a single differential bit line sense amplifier. The bit line sense amplifier includes a plurality of first transistors, the base electrodes of which are connected to local bit lines of the memory cell blocks, the emitter electrodes of which are commonly connected to corresponding main bit lines, and the collector electrodes of which are connected to a first power supply node, a second transistor, which forms a differential pair with each of the first transistors, the base electrode of which is applied with a reference bias potential, and the emitter electrode of which is connected to the main bit lines, a current source connected between the emitter electrode of the second transistor, and a second power supply node, and a load circuit connected between the collector electrode of the second transistor and the first power supply node. The main bit lines with a heavy load can be driven by the emitters having a large driving force, and the outputs from the memory cell blocks can be sensed without going through selectors, thus attaining high-speed read access.

REFERENCES:
patent: 4618945 (1986-10-01), Sakurai et al.
patent: 5148395 (1992-09-01), Sowards
T. S. Yang et al., "A 4nsec 4kx1bit Two-Port BiCMOS SRAM", IEEE 1988 CCIC, 4.7.1-4.7.4.

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