LDD spacers in MOS devices with double spacers

Details LDD spacers in MOS devices with double spacers LDD spacers in MOS devices with double spacers

1998-04-06

1999-05-18

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257401, 257900, 257336, H01L29/76;27/088

Patent

active

059052937

ABSTRACT:
In MOSFET devices with a pair of gate conductor stacks formed of a gate oxide layer, a gate electrode layer and a dielectric cap layer, LDD regions are formed by ion implanting lightly doped regions in the surface of the substrate. The LDD regions are self-aligned with the gate conductor stacks. Then form first dielectric spacers of a first dielectric material on the sidewalls of the gate conductor stacks; and form second dielectric spacers of a second dielectric material on the sidewalls of the first dielectric spacers adjacent to the gate conductor stacks thereby forming double sidewall spacers. Form fully doped regions ion implanted into the surface of the substrate self-aligned with the double sidewall spacers. The fully doped regions are self-aligned with the first and second dielectric spacers formed on the gate conductor stacks. The device is covered with a blanket dielectric layer formed by LPCVD from a TEOS source. Above the new dielectric layer, a mask is formed with a contact opening therethrough over a contact region. Then etch away the second dielectric spacers below the contact opening to form self-aligned contact regions reaching down to the substrate between the first dielectric spacers.

REFERENCES:
patent: 5208472 (1993-05-01), Su et al.
patent: 5240872 (1993-08-01), Motonami et al.
patent: 5468665 (1995-11-01), Lee et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5498555 (1996-03-01), Lin
patent: 5702972 (1997-12-01), Tsai et al.

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