Method of making an asymmetrical IGFET and providing a field die

Details Method of making an asymmetrical IGFET and providing a field die Method of making an asymmetrical IGFET and providing a field die

1997-08-25

1999-05-18

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438307, 438595, H01L21/336

Patent

active

059045299

ABSTRACT:
A method of making an asymmetrical IGFET and isolating active regions is disclosed. The method includes providing a semiconductor substrate with an active region and a field region, wherein the active region includes a source region and a drain region, and the active region is adjacent to the field region, forming a dielectric layer over the substrate, forming a first etch mask over the dielectric layer, etching a selected portion of the dielectric layer beneath an opening in the first etch mask, wherein a first unetched portion of the dielectric layer provides a field dielectric over the field region, a second unetched portion of the dielectric layer provides a drain-protect dielectric over the drain region, and the dielectric layer is removed above the source region, forming a gate insulator on a portion of the active region outside the drain-protect dielectric, depositing a gate material over the drain-protect dielectric and the gate insulator, polishing the gate material so that a portion of the gate material over the drain-protect dielectric is removed, forming a second etch mask over the gate material, etching the gate material beneath an opening in the second etch mask to remove a portion of the gate material over the source region, wherein an unetched portion of the gate material forms a gate, and a sidewall of the gate is adjacent to a sidewall of the drain-protect dielectric, implanting a dopant into the active region during a first implant step, wherein a greater concentration of the dopant is implanted in the source region than in the drain region due to the drain-protect dielectric, and forming a source in the source region and a drain in the drain region. Advantageously, the dielectric layer provides both the field dielectric and the drain-protect dielectric to reduce process steps, and the IGFET has low source-drain resistance and reduces hot carrier effects.

REFERENCES:
patent: 4225875 (1980-09-01), Ipri
patent: 4258465 (1981-03-01), Yasui et al.
patent: 4272881 (1981-06-01), Angle
patent: 4597827 (1986-07-01), Nishitani et al.
patent: 4737828 (1988-04-01), Brown
patent: 4927777 (1990-05-01), Hsu et al.
patent: 5073514 (1991-12-01), Ito et al.
patent: 5132753 (1992-07-01), Chang et al.
patent: 5171700 (1992-12-01), Zamanian
patent: 5200358 (1993-04-01), Bollinger et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5296398 (1994-03-01), Noda
patent: 5349225 (1994-09-01), Redwine et al.
patent: 5364807 (1994-11-01), Hwang
patent: 5366915 (1994-11-01), Kadama
patent: 5397715 (1995-03-01), Miller
patent: 5424229 (1995-06-01), Oyamatsu
patent: 5424234 (1995-06-01), Kwon
patent: 5436482 (1995-07-01), Ogoh
patent: 5444024 (1995-08-01), Anjum et al.
patent: 5451807 (1995-09-01), Fujita
patent: 5510279 (1996-04-01), Chien et al.
patent: 5512503 (1996-04-01), Hong
patent: 5512506 (1996-04-01), Chang et al.
patent: 5518940 (1996-05-01), Hodate et al.
patent: 5521417 (1996-05-01), Wada
patent: 5525552 (1996-06-01), Huang
patent: 5547885 (1996-08-01), Ogoh
patent: 5547888 (1996-08-01), Yamazaki
patent: 5550084 (1996-08-01), Anjum et al.
patent: 5578509 (1996-11-01), Fujita
patent: 5580815 (1996-12-01), Hsu et al.
patent: 5585293 (1996-12-01), Sharman et al.
patent: 5585658 (1996-12-01), Mukai et al.
patent: 5607869 (1997-03-01), Yamazaki
patent: 5643825 (1997-07-01), Gardner et al.
patent: 5648286 (1997-07-01), Gardner et al.
patent: 5654215 (1997-08-01), Gardner et al.
patent: 5656518 (1997-08-01), Gardner et al.
patent: 5672531 (1997-09-01), Gardner et al.
patent: 5677224 (1997-10-01), Kadosh et al.
patent: 5801088 (1998-09-01), Gardner et al.
Codella et al; U.S. Statutory Invention Registration H986; Nov. 05, 1991.
U.S. Patent Application Serial No. 08/884,802, filed Jun. 30, 1997, entitled "Method Of Making An IGFET And A Protected Resistor With Reduced Processing Steps," by Gardner et al. (copy encloded), pending.
U.S. Patent Application Serial No. 08/781,092, filed Jan. 8,1997, entitled "Method Of Forming Lightly Doped Drain Region And Heavily Doping A Gate Using A Single Implant Step", by Gardner et al. (copy enclosed), pending.
U.S. Patent Application Serial No. 08/682,238 filed Jul. 17, 1996 entitled "Method For Fabricating of a Non-Symmetrical Transistor" by Gardner et al. (copy not enclosed), pending.
IBM Technical Disclosure Bulletin, "Process for Making Very Small, Asymmetric, Field-Effect Transistors", vol. 30, No. 3, Aug. 1987, pp. 1136-1137 (XP 000671026).
IBM Technical Disclosure Bulletin, "Low Series Resistance Source by Spacer Methods", vol. 33, No. 1A, Jun. 1, 1990, pp. 75-77 (XP 000120044).

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