Self-aligned dual damascene arrangement for metal interconnectio

Details Self-aligned dual damascene arrangement for metal interconnectio Self-aligned dual damascene arrangement for metal interconnectio

1999-01-04

2000-11-28

Nelms, David

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438633, 438634, 438637, 438672, 438752, 438762, H01L 214763

Patent

active

061535141

ABSTRACT:
A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

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