Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-06-21
2000-11-28
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438589, H01L 21336
Patent
active
061534757
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
For many electronic systems, memories are required into which the data are fixedly written in digital form. Memories of this sort are known as, among other designations, fixed-value memories, read memories, or read-only memories.
For large quantities of data, such as in particular the digital storage of music, plastic discs called compact discs, which are coated with aluminum, are often used as read memories. These discs comprise in their coating two kinds of punctiform recesses, allocated to the logical values zero and one. The information is stored digitally in the arrangement of these recesses.
In order to read the data stored on a compact disc, the disc is mechanically rotated in a read apparatus. The punctiform recesses are scanned using a laser diode and a photocell. Typical scan rates are thereby 2.times.40 kHz. Approximately 5 Gbits of information can be stored on a plastic disc.
The read apparatus comprises moving parts that are subject to mechanical wear, require a comparatively large volume, permit only a relatively slow data access, and have a large current consumption. In addition, the read apparatus is sensitive to vibrations, and thus has only limited suitability for mobile systems.
For the storage of smaller amounts of data, fixed-value memories based on semiconductors, in particular on silicon, are often used. During the reading out of the memory cell arrangement, the individual memory cells are selected via a wordline. The gate electrode of the MOS transistors is respectively connected with a wordline. The input of each MOS transistor is connected with a reference line and the output is connected with a bitline. During the read process, it is evaluated whether or not a current is flowing through the transistor. The logical values zero and one are allocated accordingly.
Technologically, the storage of a zero and a one in these fixed-value memories is effected in that, in memory cells in which the logical value allocated to the state "no flow of current through the transistor" is stored, no MOS transistor is manufactured, or no conductive connection to the bitline is realized. Alternatively, the two logical values can be realized by MOS transistors that have different threshold voltages due to different implantations in the channel region.
These known silicon memories mostly have a planar construction. A minimum space requirement per memory cell is thereby required that is about 4 to 6 F.sup.2, whereby F is the smallest structural size that can be manufactured in the respective technology. Given a 0.4 .mu.m technology, planar fixed-value silicon memories are thus limited to storage densities of around 1 bit/.mu.m.sup.2.
From U.S. Pat. No. 4,954,854, it is known to use vertical MOS transistors in a fixed-value memory. For this purpose, the surface of the silicon substrate is provided with hole-type trenches, adjoined at the floor by a source region, and adjoined at the substrate surface by a drain region that surrounds the trench, and along whose edges a channel region is arranged. The surface of the trench is provided with a gate dielectric, and the trench is filled with a gate electrode. In this arrangement, zero and one are distinguished in that for one of the logical values no trench is etched and no transistor is manufactured. Adjacent memory cells are insulated from one another by insulating structures arranged laterally thereto.
In the prior German patent application P 19 514 834.7, a fixed-value memory cell arrangement was proposed that has first memory cells that comprise a vertical MOS transistor, and that has second memory cells that comprise no vertical MOS transistor. The memory cells are thereby arranged along opposite edges of strip-type insulation trenches that run in parallel. The memory cell arrangement can be realized with a space requirement of 2F.sup.2 per memory cell, whereby F is the minimum structural size of the respective technology.
SUMMARY OF THE INVENTION
The present invention is based on the problem of indicating a method for manu
REFERENCES:
patent: 4954854 (1990-09-01), Dhong et al.
patent: 5330927 (1994-07-01), Lee
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Hofmann Franz
Krautschneider Wolfgang
Reisinger Hans
VON Basse Paul-Werner
Willer Josef
Chaudhari Chandra
Siemens Aktiengesellschaft
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