Method of fabricating dual gate structure of embedded DRAM

Details Method of fabricating dual gate structure of embedded DRAM Method of fabricating dual gate structure of embedded DRAM

1998-11-16

2000-11-28

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438238, 438239, 438241, 438253, 438396, 437 60, 437193, 437200, 437919, H01L 218244

Patent

active

061534595

ABSTRACT:
A method of fabricating a dual gate of embedded DRAM forms a conductive layer on a substrate having a memory cell region and a logic circuitry. A gate structure is then formed on the substrate of the memory cell region and the conductive layer of the logic circuitry is removed by patterning the conductive layer. A polysilicon layer is then deposited and a dual gate structure is formed by patterning the polysilicon layer, and simultaneously, a polysilicon spacer is formed on the sidewall of the gate structure in the logic circuitry. The polysilicon spacer is then removed. An insulated spacer is formed on the sidewall of the gate structure and the dual gate structure, and a silicide layer is formed on the dual gate structure and the exposed substrate of the logic circuitry.

REFERENCES:
patent: 5668035 (1997-09-01), Fang et al.
patent: 5677227 (1997-10-01), Yang et al.
patent: 6015732 (2000-01-01), Williamson et al.
patent: 6037222 (2000-03-01), Huang et al.

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