Method of fabricating ultra shallow junction CMOS transistors wi

Details Method of fabricating ultra shallow junction CMOS transistors wi Method of fabricating ultra shallow junction CMOS transistors wi

1998-10-13

2000-11-28

Thomas, Tom

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438197, 438199, 438227, 438229, 438230, 438231, 438303, 438305, 438306, 438307, 257369, 257408, H01L 21334, H01L 21335, H01L 21336, H01L 218232, H01L 218238

Patent

active

061534552

ABSTRACT:
A method of developing a transistor, such as a complimentary MOS (CMOS) transistor, that includes lightly doped drain (LDD) regions which uses disposable spacers, and includes the step of adding an oxide spacer etch after a disposable nitride spacer removal and between source/drain implant and LDD implant. Because of this additional step, an ultra shallow LDD implant can be achieved. Moreover, uniformity of the depth of the junction is improved as the non-uniformity of the screen/liner oxide is eliminated.

REFERENCES:
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 4978626 (1990-12-01), Poon et al.
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5069747 (1991-12-01), Cathey et al.
patent: 5286664 (1994-02-01), Horiuchi
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5536684 (1996-07-01), Dass et al.
patent: 5580804 (1996-12-01), Joh
patent: 5610088 (1997-03-01), Chang et al.
patent: 5654213 (1997-08-01), Choi et al.
patent: 5693974 (1997-12-01), Hsu et al.
patent: 5780350 (1998-07-01), Kapoor
patent: 5783458 (1998-07-01), Kadosh et al.
patent: 5786257 (1998-07-01), Wen
patent: 5824588 (1998-10-01), Liu
patent: 5847428 (1998-12-01), Fulford, Jr. et al.
patent: 5880006 (1999-03-01), Lin et al.
patent: 5904529 (1999-05-01), Gardner et al.
patent: 5970353 (1999-10-01), Sultan
Silicon Processing for the VLSI Era--vol. 111, "Shallow Trench and Refill Isolation" (date unknown), pp. 367-373.

Affiliated with

Also associated with

Rating

Method of fabricating ultra shallow junction CMOS transistors wi does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating ultra shallow junction CMOS transistors wi, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating ultra shallow junction CMOS transistors wi will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1724463