Staggered pad array

Details Staggered pad array Staggered pad array

1996-11-01

2000-03-14

Arroyo, Teresa M.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Configuration or pattern of bonds

257695, 257784, H01L 2348, H01L 2352

Patent

active

060376694

ABSTRACT:
A semiconductor die assembly of this invention includes a lead system in which the leads are arranged in a radial pattern. That is, in a group of leads associated with a single side of a semiconductor die, leads which are furthest from the middle are most angled from the perpendicular. The semiconductor die includes an outer row of bond pads which are located proximate to the edge of the semiconductor die and an inner row of bond pads, parallel to the first row and located toward the interior of the semiconductor die surface. In one embodiment, one of the rows of bond pads is regularly spaced, while the other row of bond pads is variably spaced. The bond pads of the variably spaced row are positioned such that a bond wire which connects a bond pad of the inner row to its associated lead will pass substantially medially between the centers of the two closest bond pads of the outer

REFERENCES:
patent: 5153507 (1992-10-01), Fong et al.
patent: 5355019 (1994-10-01), Fuchs
Harmon, "Wire Bonding . . . " Dec. 1992 IEEE Transactions.

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