Static information storage and retrieval – Read/write circuit – Precharge
Patent
1997-02-10
1998-11-24
Nguyen, Tan T.
Static information storage and retrieval
Read/write circuit
Precharge
3652385, G11C 700
Patent
active
058417150
ABSTRACT:
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
REFERENCES:
patent: 3691534 (1972-09-01), Varadi et al.
patent: 3740723 (1973-06-01), Beausoleil et al.
patent: 3771145 (1973-11-01), Wiener
patent: 3882470 (1975-05-01), Hunter
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4222112 (1980-09-01), Clemmons et al.
patent: 4286321 (1981-08-01), Baker et al.
patent: 4421996 (1983-12-01), Chuang et al.
patent: 4513374 (1985-04-01), Hooks, Jr.
patent: 4562435 (1985-12-01), McDonough et al.
patent: 4646270 (1987-02-01), Voss
patent: 4649516 (1987-03-01), Chung et al.
patent: 4658381 (1987-04-01), Reed et al.
patent: 4748320 (1988-05-01), Yorimoto et al.
patent: 4750839 (1988-06-01), Wang et al.
patent: 4757473 (1988-07-01), Kurihara et al.
patent: 4758993 (1988-07-01), Takemae
patent: 4802135 (1989-01-01), Shinoda et al.
patent: 4803621 (1989-02-01), Kelly
patent: 4811202 (1989-03-01), Schabowski
patent: 4833650 (1989-05-01), Hirayama et al.
patent: 4860198 (1989-08-01), Takenaka
patent: 4932002 (1990-06-01), Houston
patent: 4940909 (1990-07-01), Mulder et al.
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 4970418 (1990-11-01), Masterson
patent: 4982368 (1991-01-01), Arimoto
patent: 5012408 (1991-04-01), Conroy
patent: 5018110 (1991-05-01), Sugiyama et al.
patent: 5034917 (1991-07-01), Bland et al.
patent: 5040153 (1991-08-01), Fung et al.
patent: 5051889 (1991-09-01), Fung et al.
patent: 5051954 (1991-09-01), Toda et al.
patent: 5051955 (1991-09-01), Kobayashi
patent: 5056060 (1991-10-01), Fitch et al.
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5093807 (1992-03-01), Hashimoto et al.
patent: 5175831 (1992-12-01), Kumar
patent: 5179670 (1993-01-01), Farmwald et al.
patent: 5226009 (1993-07-01), Arimoto
patent: 5270973 (1993-12-01), Guillemaud et al.
patent: 5276641 (1994-01-01), Sprogis et al.
patent: 5297091 (1994-03-01), Blake et al.
patent: 5301155 (1994-04-01), Wada et al.
patent: 5301162 (1994-04-01), Shimizu
patent: 5353427 (1994-10-01), Fujishima et al.
patent: 5377149 (1994-12-01), Caultier
patent: 5390149 (1995-02-01), Vogley et al.
patent: 5404327 (1995-04-01), Houston
patent: 5410512 (1995-04-01), Takase et al.
patent: 5590081 (1996-12-01), Shimizu
Tsen-Shau Yang, "A 4-ns 4K X 1-bit Two-Port BiCMOS SRAM", Oct. 1988, vol. 23, No. 5, pp. 1030-1040.
Richard E. Matick, "Comparison of Memory Chip Organizations vs Reliability in Virtual Memories", Jun. 22-24, 1982, pp. 223-227.
Horowitz, et al. "MIPS-X: A 20-MIPS Peak, 32-bit Microprocessor with On-Chip Cache", vol. SC-22, No. 5, Oct. 1987, pp. 790-799.
S. K. Kwon, et al. "Memory Chip Organizations for Improved Reliability in Virtual Memories", IBM Tech. Disclosure Bulletin, Vo. 25, No. 6, Nov. 1982, pp. 2952-2957.
Steve Gumm, et al. "Unravelinlg the intricacies of dynamic RAMs", Designer's Guide dynamic RAMs Part 1, Mar. 30, 1989, pp. 155-166.
Farmwald Michael
Horowitz Mark
Nguyen Tan T.
Rambus Inc.
LandOfFree
Integrated circuit I/O using high performance bus interface does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit I/O using high performance bus interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit I/O using high performance bus interface will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1710699