Voltage clamping circuit for semiconductor devices

Details Voltage clamping circuit for semiconductor devices Voltage clamping circuit for semiconductor devices

1996-12-19

1999-06-22

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327308, 327314, 327321, 327325, H03K 508

Patent

active

059146265

ABSTRACT:
A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

REFERENCES:
patent: 5361001 (1994-11-01), Stolfa
patent: 5450030 (1995-09-01), Shin et al.

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