Method for manufacturing semiconductor substrate having buck tra

Details Method for manufacturing semiconductor substrate having buck tra Method for manufacturing semiconductor substrate having buck tra

1995-10-27

1997-03-18

Fourson, George

Fishing, trapping, and vermin destroying

437152, 437984, H01L 2176

Patent

active

056122462

ABSTRACT:
A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area diposed on an upper single crystalline silicon layer. The method characterized in that a spacer is formed on a portion of the bulk transistor area which covers a sidewall of the SOI transistor area, a first conductive well is formed in the lower single crystalline silicon layer and a well oxide layer is formed over the first conductive well region, a second conductive well is formed in the lower single crystalline silicon layer between the SOI transistor layer and the first conductive well, and the first conductive well is rediffused.

REFERENCES:
patent: 4889829 (1989-12-01), Kawai
patent: 4929565 (1990-05-01), Parillo
patent: 5476809 (1995-12-01), Kobayashi
patent: 5547886 (1996-08-01), Harada

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