Method for patterning a polysilicon gate with a thin gate oxide

Details Method for patterning a polysilicon gate with a thin gate oxide Method for patterning a polysilicon gate with a thin gate oxide

1998-09-28

2000-03-14

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438738, 438743, 438744, H01L 2100

Patent

active

060372664

ABSTRACT:
A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:

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patent: 5767018 (1998-06-01), Bell
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