Semiconductor memory device and fabrication thereof

Details Semiconductor memory device and fabrication thereof Semiconductor memory device and fabrication thereof

1997-08-29

1999-06-08

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438262, 438546, H01L 218236

Patent

active

059111062

ABSTRACT:
A fabrication process of a mask ROM is disclosed, which process is effective to suppress the occurrence of punch-through of a memory cell transistor. According to the process, the surface of a P conductivity-type silicon substrate is subjected to thermal oxidation to grow oxides to form a pad oxide film. A silicon nitride film, which acts as an oxidation resisting film, is deposited on the pad oxide film. A resist is formed on the silicon nitride film. The resist has openings where bit lines are to extend. Using the resist as a mask, the silicon nitride film is selectively etched away. Using the resist as a mask, ions of arsenic (As) are introduced by ion implantation to the substrate for formation of N conductivity-type diffusion regions in the subsequent thermal oxidation. These N conductivity-type diffusion regions act as the bit lines. Using the resist as a mask, ions of boron (B) are introduced by ion implantation for formation of P.sup.+ conductivity-type diffusion regions in the subsequent thermal oxidation. During the thermal oxidation, the P.sup.+ conductivity-type diffusion regions surround the N conductivity-type diffusion regions, and field oxide regions are formed on the N conductivity-type diffusion regions. The silicon nitride layer and the pod oxide layer thereunder are removed. Gate oxide regions are formed. Word lines of a polycide are formed on the gate oxides regions. The word lines extend orthogonal to a direction in which the N conductivity-type diffusion regions (bit lines) extend.

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