Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-15
2000-03-14
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438282, 438529, H01L 218246
Patent
active
060372273
ABSTRACT:
A mask ROM uses a bit line structure having a vertically graded dopant distribution or a distinct two level dopant distribution. A bit line might include a highly doped region buried deeply within the substrate that is connected to a comparatively lightly doped region formed above the more highly doped region. The vertical structure of the bit line allows the bit line to be less resistive than the simpler shallow bit line structure conventionally used. The vertical structure (i.e., the two level or graded structure) of the bit line allows the bit line to have a lower doping immediately adjacent the channel region, which reduces the likelihood of punchthrough. The deeper, highly doped portions of the bit line are narrow and laterally confined so that well defined antipunchthrough implantations can be formed which lie between but separated from the more highly doped portions of the bit lines. This aspect of the structure reduces the likelihood of punchthrough while limiting the extent of overlap between the buried bit lines and the antipunchthrough implantation.
REFERENCES:
patent: 4649629 (1987-03-01), Miller et al.
patent: 4717684 (1988-01-01), Katto et al.
patent: 5470774 (1995-11-01), Kunitou
patent: 5538914 (1996-07-01), Chiu et al.
patent: 5670402 (1997-09-01), Sogawa et al.
Chaudhari Chandra
United Microelectronics Corp.
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