Method of increasing the surface area of a DRAM capacitor struct

Details Method of increasing the surface area of a DRAM capacitor struct Method of increasing the surface area of a DRAM capacitor struct

1998-07-24

2000-03-14

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438398, H01L 218242

Patent

active

060372206

ABSTRACT:
A method of creating an STC structure, with increased surface area, needed for high density, DRAM designs, has been developed. The increased surface area, for the STC structure is obtained via use of HSG polysilicon sidewalls, and via use of a grated, top surface topography. A capping insulator layer is used as a hard mask, to allow formation of the HSG polysilicon sidewalls, on the sides of a storage node structure, without degradation to the top surface of the storage node structure, during the HSG polysilicon sidewall formation process. A second iteration features the creation of a storage node structure, with a grated, top surface topography, as well as HSG polysilicon sidewalls. The grated top surface topography, for the storage node structure, is obtained by forming crevices in the top surface of the storage node structure via a series of RIE procedures, using the HSG polysilicon features, and underlying capping insulator layer features, as an etch mask.

REFERENCES:
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patent: 5340763 (1994-08-01), Dennison
patent: 5444653 (1995-08-01), Nagasawa et al.
patent: 5447878 (1995-09-01), Park et al.
patent: 5663085 (1997-09-01), Tanigawa
patent: 5930625 (1999-07-01), Lin et al.

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